CES for Expedition PCB (v2007)

Duration: 2 Days
Course Part Number: 236552

Course Overview
Description
CES is a Constraint Editor System, which gives you the ability to define and refine design constraints in a common environment that is accessible from many Mentor Graphics Corporation front-end and back-end design systems. This course is designed to cover all the necessary skills required to use CES efficiently and effectively in DxDesigner-Expedition and Design Capture/Design View-Expedition flows. The labs in the course allow you to gain hands-on experience with the tool, defining both mechanical and high-speed constraints to meet today’s challenging PCB designs.

You will learn how to

• Define the main concepts and constraints hierarchy of CES.
• Enable CES as a constraint system in DxDesigner-Expedition and Design Capture/Desig
• View-Expedition flows.
• Find and filter data in the design database.
• Navigate and manipulate the constraints hierarchy.
• Use the spreadsheets, toolbars, preferences, and options efficiently.
• Reuse already defined constraints in other designs using Constraint Templates.
• Partition the design data using Net Classes, Constraint Classes and Schemes.
• Set up mechanical constraints such as trace widths, via assignments and clearances.
• Assign physical high-speed constraints including minimum and maximum delays, matche
• delays, delay formulas, custom and complex topologies, differential pairs, and parallelism rules to nets or group of nets.
• Auto-route the constrained nets and evaluate the routing results.

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using CES software. Hands-on lab topics include:

• Enabling CES and synchronizing databases in the following design flows.
  • Dx Designer to Expedition Flo
  • Design Capture/Design View to Expedition Flow
• User Interface
  • Customizing the Windows Display
  • Using the CES Browser and the Spreadsheets
  • Editing Data in Spreadsheets Interfacing with the PCB Data
• Setting Up Mechanical Constraints
  • Creating Schemes
  • Creating and Populating Net Classes
  • Setting up Trace and Via Properties
  • Setting up Clearance Rule
  • Setting up Z-Clearances
• Setting up Physical High-Speed Constraints
  • Creating hierarchy of Constraint Classes
  • Assigning Standard, Custom, and Complex Topologies for a Net
  • Setting up Differential Pair Constraints
  • Setting up Maximum and Minimum delays, delay formulas, and Matched Length groups.
  • Setting up Parallelism Rule
  • Auto route the nets constrained with both mechanical and high-speed requirements.
• Constraints Reuse
  • Importing Constraint Templates
  • Testing Constraint Templates
  • Assigning Constraint Templates

Audience

• PCB Design Engineers
• PCB layout personnel
• Signal Integrity Engineers
• Design managers
• Project Managers

Prerequisites

• Familiarity with concepts of PCB design and technology
• Familiarity with Windows 98, NT, 2000, XP or UNIX operating systems

Key Topics

• CES Overview
• CES in the flow
• CES User Interface
• Net Classes and Schemes
• Setting up Mechanical Constraints
• Constraint Classes
• Net Properties and Differential Pairs
• Delays and Parallelism
• Constraint Templates

For more information:

InnoFour BV
Twentepoort Oost 61-02
7609 RG ALMELO
The Netherlands
tel +31 546 454 530
fax +31 546 453 006
training@innofour.com