I/O Designer
Duration: 2 Days
Course Part Number: 221966
Description
As the FPGA devices grew larger, it is harder to maintain consistency between the FPGA and PCB design flows. I/O Designer bridges the gap between the two design flows. This course offered by Mentor Graphics teaches you how to manage the data and monitor the changes between the two design flows while maintaining consistency. Both the lectures and hands-on labs provide students with skills necessary to use the tool efficiently in the design process.
You will learn how to
- Use I/O Designer in different design scenarios.
- Create an I/O Designer database.
- Assign signals read in from a HDL file to the FPGA device pins.
- Do automatic unraveling of signals and buses based on the PCB floorplan
- Create symbols using different fracturing schemes.
- Export the created symbols to a schematic tool.
- Update and synchronize the changes between the two design flows.
- Manage the database in a team design using version control mechanisms.
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using I/O Designer software. Hands-on lab topics include:
- I/O Designer GUI and software configuration.
- Setup of FPGA/PCB projects in various design environments and design styles .
- Defining the FPGA I/O design either in I/O Designer or the FPGA flow or the PCB flow.
- Generation of the schematic sheets and symbols and the FPGA PCB mapping data.
- Update and synchronize changes between the two design flows.
- Manage the database in a team design using version control mechanisms.
Prerequisites
The students who attend this course should have a general understanding of PCB and FPGA design flows. They should also have knowledge of schematic capture and PCB layout.
Audience
- PCB Design Engineers
- FPGA Design Engineers
- System Design Engineers
Key Topics
- Introduction to I/O Designer
- User Interface
- Creating a New Database
- Assigning IO Pins
- Creating and Exporting Symbols
- Synchronization between PCB and FPGA flows
- Designing with Multiple Users
- Discussion of FPGA specific library issues
- Reuse existing symbols with I/O Designer
- Defining various power/config pin scenarios
- How to deal effectively with differential pair signals
- Redesign of a pre – I/O Designer design
- Timing constraints and SSO checking
For more information:
InnoFour BV
Twentepoort Oost 61-02
7609 RG ALMELO
The Netherlands
tel +31 546 454 530
fax +31 546 453 006
training@innofour.com
