Verification Academy

The Verification Academy, a unique, highly-accessible approach to meet the educational needs of verification engineers. The goals of this online academy are to provide the skills necessary to mature an organization’s advanced functional verification process capabilities. To this end, the Verification Academy provides a methodological bridge between high-level value propositions (related to advanced verification technology) and the low-level details (related to specific tool and verification language details). The Verification Academy, which features Harry Foster as the primary instructor, can be accessed around the clock at: http://verification-academy.mentor.com/.

“The Verification Academy provides well-sized, informative presentations on some of the advanced verification techniques used by Icera, from high-level processes of interest to managers, through to technical material for hands-on engineers,” said Kevin Dewar, Silicon Engineering Director, Icera Semiconductor. “We expect to use the material to develop the skills of engineers new to these techniques, and to refine the skills of experienced engineers.”

About the Verification Academy: Where Education Meets Opportunity

A web seminar to introduce the Verification Academy to prospective users : http://www.mentor.com/products/fv/events/verification-academy-webseminar.

Currently the Verification Academy contains the following modules with additional modules planned for release over the coming year:

• UVM/OVM Online Methodology Cookbook

  The UVM/OVM Online Methodology Cookbook provides the most comprehensive and up-to-date guidelines for effective deployment of both UVM (Universal Verification Methodology) and OVM (Open Verification Methodology). Online documentation comes with downloadable examples to help you quickly learn the best ways to develop your verification environment and VIP. 

• Basic UVM (Universal Verification Methodology)

  This session gives an overview of UVM, describes the motivation and benefits, and introduces some technical highlights. In addition walks through a short, simple example to get you started with UVM. Also discusses how to connect a UVM testbench to the DUT and how to share information around the testbench using the configuration database. Additional topics include: connecting components, transactions, sequences and tests, monitors and subscribers and lastly, message reporting in UVM, with simple ways in which reporting can be customized. 

• Basic OVM (Open Verification Methodology)

  The goal of the OVM Basics module is to raise your skill level to the point where you have sufficient confidence in your own technical understanding. Thus, giving you the confidence required to start the process of adopting advanced functional verification techniques. This module is primarily aimed at existing VHDL and Verilog engineers or managers who recognize they have a functional verification problem but have little or no experience with constrained-random verification or object-oriented programming.

• Advanced OVM & UVM

  The goal of the Advanced OVM (& UVM) module is to improve your understanding of OVM so you can move beyond basic block-level testbenches. Building on the concepts discussed in the Basic OVM module, you will learn how to assemble multi-level environments with layered stimulus sequences to handle more complex verification challenges.

• Intelligent Testbench Automation

  Achieving coverage closure is consistently identified as one of the most difficult challenges facing electronics product development teams. Over the past few years, the industry’s leading functional verification engineering teams have begun turning to a new and emerging technology called Intelligent Testbench Automation (“iTBA”). iTBA combines the high quality of directed testing with the high quantity of constrained random testing, and can be easily integrated into existing verification environments. This module provides a complete introduction to iTBA, showing how you can achieve your coverage goals >10X faster, leaving you the option to reduce your verification time, expand your coverage.

•  Verification Planning and Management

  The verification of any design of size is a daunting task that requires successful forethought in the form of formulating, architecting, strategizing and documenting an overall verification blueprint. The value of creating such a blueprint at the start of a project has been proven out thru gathered metrics of successful projects. This verification planning and management (VPM) module is a 3 part, 90 min introduction towards creating such a verification blueprint.

• Assertion-Based Verification (ABV)

  With the advent of standardized assertion languages and assertion libraries, the industry has recently witnessed an increased interest in adopting assertion-based techniques. This module introduces a set of steps for advancing an organization’s ABV skills, infrastructure, and metrics for measuring success while identifying process areas requiring improvement. Simulation-based ABV methods are used throughout the methodology introduced. In addition, formal-based ABV techniques are also highlighted for selected verification hotspots.

• FPGA Verification Capabilities

  The change in FPGA capabilities has resulted in the emergence of advanced FPGA system-on-chip (SoC) solutions, which includes the integration of third-party IP, DSPs, and multiple microproces-sors—all connected through advanced, high-speed bus protocols. Accompanying these changes has been an increase in design and verification complexity, which traditional FPGA flows are generally not prepared to address. This module introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.

• (CDC) Clock-Domain Crossing Verification Module

  For the past dozen or so years, static timing analysis has served the industry well by ensuring that all synchronous design blocks will not violate any of the design’s setup and hold-timing constraints. However, with the convergence of multiple applications into a complex SoC (such as digital-audio, video, wireless, and networking), as well as the industry’s adoption of an IP reuse strategy, project teams are now faced with a new set of clocking verification challenges that are not addressed by static timing analysis. This module introduces clock-domain crossing concepts and provides insight into understanding the challenges encountered in complex SoCs.

• Evolving Verification Capabilities

  Ensuring functional correctness on RTL designs continues to pose one of the greatest challenges for today’s ASIC, FPGA and SoC design teams. This module provides a common framework for all advanced functional verification modules contained within the Verification Academy. A simple Evolving Capabilities model is presented, which can be used as a tool for assessing an organization’s functional verification process capabilities.

• Acceleration of SystemVerilog Testbenches with Co-Emulation

  This module on Acceleration of SystemVerilog Testbenches with Co-Emulation will give you the confidence required to start the process of investigating and creating a single testbench environment that can be used for both simulation as well as hardware-assisted acceleration. The module is primarily aimed at existing SystemVerilog H/W engineers or managers who recognize they have a functional verification throughput problem but have little or no experience with using emulation as a means for accelerating SystemVerilog testbench environments.

• SystemC Testbench

  This module advocates that functional verification through modern SystemC testbenches paired with co-emulation enables further verification productivity improvements in terms of raw performance. SystemC simulation combined with co-emulation will deliver dramatic speedup of execution of verification. This module on Acceleration of SystemC and TLM-2.0 testbenches with Co-Emulation will give you the confidence required to start the process of investigating and creating a single testbench environment that can be used for both simulation as well as hardware-assisted acceleration.