Electronic System Level Design

Achieving Optimal Designs through ESL Methodologies
Today’s advanced designs have grown too massive and complex to cost-effectively design and verify using traditional RTL methodologies alone. Electronic System Level (ESL) design methodologies address this complexity problem by elevating design to a higher level of abstraction. This relieves hardware designers from the design errors caused by the overwhelming detail of lower-level methodologies and offers much shorter and efficient design cycles.

New mobile and consumer electronics require the convergence of wireless and multimedia into a single optimized chip. Numerous new hardware blocks need to be designed and integrated, all of which requires effective software integration with hardware. The trend toward increasing complexity has led to more ASIC re-spins, lost revenue from missed design deadlines, and sub-optimal systems that are larger, slower or consume more power than required. Leveraging ESL for early system level optimization ensures the appropriate architectural decisions have been made and meet specifications.

ESL Design Tasks

ESL Design and Verification
Mentor provides ESL tools and methodologies that can be deployed to architect and validate hardware and software, ensuring an optimal system is built correctly the first time. Learn More ►
Product Demo: Efficient Model Creation for Transaction-Level Methodologies

High Level Synthesis
As design complexity pushes traditional RTL design and verification to their limits, High Level Synthesis reduces the manual effort required to create and verify synthesizable RTL code. Learn More ►
Product Demo: Catapult C Synthesis

 
ESL Design Resources

Transaction Level Modeling
Transaction level modeling (TLM) provides an abstract design methodology supporting modeling, validation analysis and implementation processes. TLM is one of the key ESL concepts that allows modeling communication at a higher level while abstracting hardware signals, cycles and data structures. More ►

Partners and Standards
Partnering with a variety of different silicon vendor and flow partners allows Catapult C Synthesis to be used by ASIC and FPGA hardware designers in today’s leading wireless, video, and image processing applications. More ►

Catapult Industry Solutions
Catapult C broadband wireless, video, image processing solutions. More ► 

Training
The courses have been tailored for audiences with varying backgrounds - from algorithm research and implementation teams to production quality hardware design teams.

• Catapult C
• C++ for Hardware Design
• C++ Coding Guidelines for Catapult C
• More ► 

High Level Synthesis On-Demand Web Seminar

Learn how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms.
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