ESL Design & Verification

System development faces significant challenges to integrate and understand the combined impact of the hardware and software architecture on system power, performance and functionality. The most common approach today is to develop the hardware and software features in isolation, integrating and testing at the end of the design cycle. As a result the opportunity to make architectural modifications is lost.

Key questions to be answered at the architectural level:

• Does it deliver the necessary functionality and meet user expectations?
• Do I understand and can I quantify the performance goals for timing and power consumption?
• Can I implement the system?

Transaction Level Modeling (TLM)

Transaction Level Modeling (TLM) is one of the key ESL concepts that allows modeling communication at a higher level while abstracting hardware signals, cycles and data structures. Learn more our TLM solutions ► 

Products

Vista Architect
Vista™ Architect is a complete TLM 2.0-based solution for architecture design and exploration enable system architects and SoC designers prototype and analyze complex systems, and ensure optimized architecture, shorter implementation cycle and first time success.

Vista Design
The industry's most advanced SystemC debug toolset, providing powerful HW and C/C++ oriented views and debugging mechanisms. Vista can naturally link into any SystemC environment and kernels such as Questa, Incisive, and OSCI.

Vista Model Builder
Vista™ Model Builder facilitates TLM model creation, allowing users to efficiently create complex models using intuitive mechanisms and pre-defined modeling classes.

Visual Elite
Visual Elite™ is the state-of-the-art design and integration platform enabling designers and system architects to intuitively capture and connect SystemC, TLM 2.0 and HDL blocks into complex SoC’s and systems.

Low Power Solutions

These days everyone is concerned about power consumption. And while you’d like to tackle power as early in the design process as possible, at the end of the day it’s about balancing power with existing requirements of system functionality, performance, and manufacturability.

The Unified Power Format (UPF) provides the backbone to our low power technologies so engineers can define power based architectures, create power aware strategies, and verify low power designs throughout the TLM to GDSII flow.

Low Power Solutions ►

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