Precision RTL

Precision RTL provides an intuitive logic synthesis environment and forms the centerpiece of the Mentor Graphics vendor-independent FPGA flow.

With a rich feature set that includes advanced optimizations, award-winning analysis, and industry-leading language support, Precision RTL enables vendor-independent design, accelerates time to market, eliminates design defects, and delivers superior quality of results (QoR).

KEY FEATURES & BENEFITS
Vendor Independent Synthesis

• Support for devices from Achronix, Actel, Altera, Lattice, Quicklogic, and Xilinx
• Same constraints and language support for all device families

Excellent Quality of Results

• Meet performance and area goals quickly
• Advanced optimization and inference techniques for all vendors
• Advanced retiming algorithm to improve performance

Easy-to-Use Interface

• Improves designer efficiency
• Design Bar guides users step by step through synthesis, analysis, placement and routing

Award-Winning Analysis

• Powerful RTL and technology schematic views
• Identify problems early in the design process
  Interactive static-timing engine quickly performs "what-if" timing analysis for different scenarios

Leading Language Support

• Supports any combination of Verilog, VHDL, SystemVerilog, and EDIF formats
• Industry leading SystemVerilog support
• Supports Synopsys Design Constraints (SDC)—the ASIC industry standard

ASIC Prototyping Support

• Eases the ASIC-to-FPGA migration process
• Automatic gated clock conversion
• Conversion of DesignWare instances
• Support for ASIC timing constraints (SDC)

Datasheets

• Precision RTL PLUS
• Precision Family Brochure

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