Products A to Z - IC Design

ADiT
Fast-SPICE simulator built specifically for analog and mixed-signal applications.

ADiT Rail, enhances ADiT with power integrity (IR) and electromigration analysis capabilities.

Calibre® Automatic Waiver provides automated recognition and removal of waived design rule violations during DRC. Calibre Automatic Waivers eliminates costly time and effort from the verification process, and ensures accurate processing of all waiver information on every DRC run.

Calibre nmLVS
The industry-standard physical verification tool for layout vs. schematic comparison combines accurate circuit verification with fast runtimes and interactive debugging.

Calibre CMPAnalyzer
Calibre CMPAnalyzer enhances systematic and parametric yield at smaller process nodes by simulating the changes in thickness and resistance variability, and by using automated fill capabilities to reduce resistance variability while minimizing capacitance

Calibre DESIGNrev™

The Calibre DESIGNrev layout editor speeds full-chip design completions and tape-outs by rapidly loading, displaying and saving large GDSII and OASIS files.

Calibre Interactive™
The Calibre Interactive™ invocation GUI provides users with fast and easy access to the Calibre® tool suite, enabling designers to perform physical verification and parasitic extraction from within their familiar IC design environment.

Calibre LFD™
Calibre LFD is the first production-proven EDA tool to address the urgent issue of how to manage lithographic process variability in the early stages of design creation.

Calibre nmDRC
The industry standard for design rule checking provides fast cycle times and innovative design rule capabilities.

Calibre PERC
Industry’s only programmable electrical rule checking (PERC) tool designed to address advanced verification requirements to ensure optimal design yield and improve reliability.

Calibre RealTime

Calibre® RealTime enables on-demand Calibre signoff design rule checking (DRC) for custom and analog/mixed-signal design flows, improving both design speed and the quality of results by providing immediate feedback on design rule violations and recommended rule compliance.

Calibre RVE™
Calibre RVE™ provides a graphical results viewing environment that can be used with all Calibre tools and popular design layout tools to reduce debug time by visually identifying design errors instantly in the user’s own design environment.

Calibre xACT 3D

Calibre® xACT 3D delivers high performance parasitic RC extraction featuring the reference-level accuracy of a deterministic field solver combined with the production turnaround performance of traditional rule-based extraction tools.

Calibre xL
Full-chip, fast, and accurate extraction of frequency dependent loop inductance and loop resistance and automatically accounts for return path change with frequency. Fully integrated with Calibre nmLVS and xRC.

Calibre xRC
Calibre xRC™ offers a robust parasitic extraction tool that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation.

Calibre YieldAnalyzer
Calibre YieldAnalyzer integrates random (critical area) and systematic (critical feature) process variability analysis using model-based algorithms that automatically plug layout measurements into yield-related equations to help you identify areas of your physical design that have higher sensitivity to variations across the manufacturing process window.

Calibre YieldEnhancer
Calibre® YieldEnhancer offers an automated approach to layout enhancements that will improve yield.

Eldo Classic
Eldo Offers numerous simulation and modeling options that deliver high-performance and high-speed simulation with superior accuracy

Eldo Premier

Mentor’s new Faster-SPICE product, addresses the primary concerns of analog and mixed-signal designers, providing increased performance and capacity, especially for very large circuits, without sacrificing accuracy.

Eldo RF
Eldo RF : Transistor-level simulator for RF IC designs.

IC Station
IC Station SDL enables automated creation of layout data, while maintaining the relationship between layout and schematic, reducing design cycle time and assuring correct-by construction layout.

ICassemble
ICassemble provides a robust set of features for floor planning, top-level assembly and interactive routing.

ICgraph
ICgraph Supports an extensive set of editing functions for efficient, accurate polygon editing.

Olympus-SoC
Olympus-SoC is a complete IC design-for-variability implementation solution targeted at 65nm/45nm designs.

Pyxis Implement

Pyxis Implement, part of Mentor's new Pyxis Custom IC Design Platform, provides a highly productive environment for correct by construction layout entry and editing.

Pyxis Layout

Pyxis Layout, part of Mentor's new Pyxis Custom IC Design Platform, provides a fast and flexible environment for layout entry and editing.

Pyxis Schematic

Pyxis Schematic, part of Mentor's new Pyxis Custom IC Design Platform, provides a powerful and easy-to-use design entry environment with advanced capabilities that boost designer productivity.

Questa ADMS
Language-neutral, mixed-signal simulator that enables top-down design and bottom-up verification of multi-million gate analog/mixed-signal System-on-Chip designs.

Questa ADMS RF

Integrated RF and Mixed Signal Simulation for Complete Verification of RF-DSP Systems.

Techpubs Multimedia Foundry Partners Customer Quotes